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1 4 meg x 4 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. d49_5v.p65 C rev. 5/00 ?2000, micron technology, inc. 4 meg x 4 fpm dram 4 meg x 4 fpm dram part numbers refresh part number v cc addressing package refresh mt4lc4m4b1dj-6 3.3v 2k soj standard mt4lc4m4b1dj-6 s 3.3v 2k soj self mt4lc4m4b1tg-6 3.3v 2k tsop standard mt4lc4m4b1tg-6 s 3.3v 2k tsop self mt4lc4m4a1dj-6 3.3v 4k soj standard mt4lc4m4a1dj-6 s 3.3v 4k soj self mt4lc4m4a1tg-6 3.3v 4k tsop standard mt4c4m4a1tg-6 s 3.3v 4k tsop self mt4c4m4b1dj-6 5v 2k soj standard mt4c4m4b1dj-6 s 5v 2k soj self mt4c4m4b1tg-6 5v 2k tsop standard mt4c4m4b1tg-6 s 5v 2k tsop self mt4c4m4a1dj-6 5v 4k soj standard mt4c4m4a1dj-6 s 5v 4k soj self mt4c4m4a1tg-6 5v 4k tsop standard mt4c4m4a1tg-6 s 5v 4k tsop self mt4lc4m4b1, mt4c4m4b1 mt4lc4m4a1, mt4c4m4a1 for the latest data sheet, please refer to the micron web site: www.micronsemi.com/mti/msp/html/datasheet.html dram features ? industry-standard x4 pinout, timing, functions, and packages ? high-performance, low-power cmos silicon-gate process ? single power supply (+3.3v 0.3v or +5v 0.5v) ? all inputs, outputs and clocks are ttl-compatible ? refresh modes: ras#-only, hidden and cas#- before-ras# (cbr) ? optional self refresh (s) for low-power data retention ? 11 row, 11 column addresses (2k refresh) or 12 row, 10 column addresses (4k refresh) ? fast-page-mode (fpm) access ? 5v tolerant inputs and i/os on 3.3v devices options marking ? voltage 3.3v lc 5v c ? refresh addressing 2,048 (2k) rows b1 4,096 (4k) rows a1 ? packages plastic soj (300 mil) dj plastic tsop (300 mil) tg ? timing 50ns access -5 60ns access -6 ? refresh rates standard refresh none self refresh (128ms period) s * note: 1. the 4 meg x 4 fpm dram base number differenti- ates the offerings in one placemt4lc4m4 b1. the fifth field distinguishes various options: b1 designates a 2k refresh and a1 designates a 4k refresh for fpm drams. 2. the # symbol indicates signal is active low. *contact factory for availability part number example: mt4lc4m4b1dj **nc on 2k refresh and a11 on 4k refresh options. pin assignment (top view) v cc dq0 dq1 we# ras# **nc/ a11 a10 a0 a1 a2 a3 v cc 1 2 3 4 5 6 8 9 10 11 12 13 26 25 24 23 22 21 19 18 17 16 15 14 v ss dq3 dq2 cas# oe# a9 a8 a7 a6 a5 a4 v ss v cc dq0 dq1 we# ras# **nc/ a11 a10 a0 a1 a2 a3 v cc 1 2 3 4 5 6 8 9 10 11 12 13 26 25 24 23 22 21 19 18 17 16 15 14 v ss dq3 dq2 cas# oe# a9 a8 a7 a6 a5 a4 v ss 24/26-pin soj 24/26-pin tsop key timing parameters speed t rc t rac t pc t aa t cac t rp -5 84ns 50ns 20ns 25ns 13ns 30ns -6 110ns 60ns 35ns 30ns 15ns 40ns
2 4 meg x 4 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. d49_5v.p65 C rev. 5/00 ?2000, micron technology, inc. 4 meg x 4 fpm dram additional columns may be accessed by providing valid column addresses, strobing cas# and holding ras# low, thus executing faster memory cycles. returning ras# high terminates the page mode of operation, i.e., closes the page. dram refresh preserve correct memory cell data by maintaining power and executing any ras# cycle (read, write) or ras# refresh cycle (ras#-only, cbr, or hid- den) so that all combinations of ras# addresses (2,048 for 2k and 4,096 for 4k) are executed within t ref (max), regardless of sequence. the cbr and self refresh cycles will invoke the internal refresh counter for automatic ras# addressing. an optional self refresh mode is also available the s version. the self refresh feature is initiated by performing a cbr refresh cycle and holding ras# low for the specified t rass. the s option allows the user the choice of a fully static, low-power data reten- tion mode or a dynamic refresh mode at the extended refresh period of 128ms, or 31.25s per row for a 4k refresh and 62.5s per row for a 2k refresh, when using a distributed cbr refresh. this refresh rate can be applied during normal operation, as well as during a standby or battery backup mode. the self refresh mode is terminated by driving ras# high for a minimum time of t rps. this delay allows for the completion of any internal refresh cycles that may be in process at the time of the ras# low-to-high transition. if the dram controller uses a distributed cbr refresh sequence, a burst refresh is not required upon exiting self refresh. however, if the dram con- troller utilizes ras#-only or burst cbr refresh se- quence, all rows must be refreshed with a refresh rate of t rc minimum prior to resuming normal operation. standby returning ras# and cas# high terminates a memory cycle and decreases chip current to a reduced standby level. the chip is preconditioned for the next cycle during the ras# high time. general description the 4 meg x 4 dram is a randomly accessed, solid- state memory containing 16,777,216 bits organized in a x4 configuration. ras# is used to latch the row address (first 11 bits for 2k and first 12 bits for 4k). once the page has been opened by ras#, cas# is used to latch the column address (the latter 11 bits for 2k and the latter 10 bits for 4k; address pins a10 and a11 are dont care). read and write cycles are selected with the we# input. a logic high on we# dictates read mode, while a logic low on we# dictates write mode. during a write cycle, data-in (d) is latched by the falling edge of we# or cas#, whichever occurs last. if we# goes low prior to cas# going low, the output pins remain open (high- z) until the next cas# cycle, regardless of oe#. a logic high on we# dictates read mode, while a logic low on we# dictates write mode. during a write cycle, data-in (d) is latched by the falling edge of we# or cas#, whichever occurs last. an early write occurs when we# is taken low prior to cas# falling. a late write or read-modify-write occurs when we# falls after cas# is taken low. during early write cycles, the data outputs (q) will remain high-z regardless of the state of oe#. during late write or read-modify-write cycles, oe# must be taken high to disable the data outputs prior to applying input data. if a late write or read- modify-write is attempted while keeping oe# low, no write will occur, and the data outputs will drive read data from the accessed location. the four data inputs and the four data outputs are routed through four pins using common i/o, and pin direction is controlled by we# and oe#. the mt4lc4m4b1 and mt4lc4m4a1 must be refreshed periodically in order to retain stored data. fast page mode access page operations allow faster data operations (read, write or read-modify-write) within a row- address-defined page boundary. the page cycle is al- ways initiated with a row address strobed in by ras#, followed by a column address strobed in by cas#.
3 4 meg x 4 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. d49_5v.p65 C rev. 5/00 ?2000, micron technology, inc. 4 meg x 4 fpm dram functional block diagram C 2k refresh 4,096 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 ras# 12 12 10 no. 2 clock generator refresh controller no. 1 clock generator v dd vss 12 we# cas# 10 column- address buffer(10) row- address buffers (12) row decoder 4,096 1,024 column decoder oe# dq0 dq1 dq2 dq3 4 4 4 4 refresh counter 1,024 4,096 x 1,024 x 4 memory array sense amplifiers i/o gating data-out buffer data-in buffer complement select 4,096 row select (1 of 4096) 2,048 2,048 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 ras# 11 11 11 no. 2 clock generator refresh controller no. 1 clock generator v dd v ss 11 we# cas# 10 column- address buffer(11) row- address buffers (11) 2,048 row decoder 2,048 1,024 column decoder oe# dq0 dq1 dq2 dq3 4 4 4 4 refresh counter 1 row transfer (2 of 2) row transfer (1 of 2) 1,024 4,096 x 1,024 x 4 memory array sense amplifiers i/o gating data-out buffer data-in buffer complement select 2,048 row select (2 of 4,096) functional block diagram C 4k refresh
4 4 meg x 4 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. d49_5v.p65 C rev. 5/00 ?2000, micron technology, inc. 4 meg x 4 fpm dram absolute maximum ratings* voltage on v cc pin relative to v ss 3.3v............................................. ......... -1v to +4.6v 5v................................................ ............ -1v to +7v voltage on nc, inputs or i/o pins relative to v ss 3.3v............................................. ......... -1v to +5.5v 5v................................................ ............ -1v to +7v operating temperature, t a (ambient) .... 0c to +70c storage temperature (plastic) ............ -55c to +150c power dissipation ................................................... 1w *stresses greater than those listed under absolute maxi- mum ratings may cause permanent damage to the device. this is a stress rating only, and functional opera- tion of the device at these or any other conditions above those indicated in the operational sections of this speci- fication is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. dc electrical characteristics and operating conditions (notes: 5, 6) (v cc (min) v cc v cc (max)) 3.3v 5v parameter/condition symbol min max min max units notes supply voltage v cc 3 3.6 4.5 5.5 v input high voltage: valid logic 1; all inputs, i/os and any nc v ih 2 5.5 2.4 vcc+1 v 24 input low voltage: valid logic 0; all inputs, i/os and any nc v il -1.0 0.8 -0.5 0.8 v 24 input leakage current: any input at v in [0v v in v cc (max)] ; i i -2 2 -2 2 a all other pins not under test = 0v output high voltage: i out = -2ma v oh 2.4 C 2.4 C v output low voltage: i out = 2ma v ol C 0.4 C 0.4 v output leakage current: any output at v out [0v v out v cc (max)]; i oz -5 5 -5 5 a dq is disabled and in high-z state
5 4 meg x 4 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. d49_5v.p65 C rev. 5/00 ?2000, micron technology, inc. 4 meg x 4 fpm dram i cc operating conditions and maximum limits (notes: 1, 2, 3, 5, 6) [vcc (min) vcc vcc (max)] 3.3v 5v 2k 4k 2k 4k parameter/condition sym speed refresh refresh refresh refresh units notes standby current: ttl i cc 1 all1111ma (ras# = cas# = v ih ) standby current: cmos (non-s version only) i cc 2 all 500 500 500 500 ma (ras# = cas# = other inputs = v cc - 0.2v) standby current: cmos (s version only) i cc 2 all 150 150 150 150 a (ras# = cas# = other inputs = v cc - 0.2v) operating current: random read/write -5 110 90 140 120 average power supply current i cc 3 -6 100 80 130 110 ma 23 (ras#, cas#, address cycling: t rc = t rc [min]) operating current: fast page mode -5 110 100 110 100 average power supply current i cc 4 -6 100 90 100 90 ma 23 (ras# = v il , cas#, address cycling: t pc = t pc [min]) refresh current: ras#-only -5 110 90 140 120 average power supply current i cc 5 -6 100 80 130 110 ma (ras# cycling, cas# = v ih : t rc = t rc [min]) refresh current: cbr -5 110 90 140 120 average power supply current i cc 6 -6 100 80 130 110 ma 4, 7 (ras#, cas#, address cycling: t rc = t rc [min]) refresh current: extended (s version only) all 300 300 300 300 a 4, 7 average power supply current: cas# = 0.2v or i cc 7 cbr cycling; ras# = t ras (min); we# = v cc - 0.2v; a0-a11, oe# and d in = v cc - 0.2v or 0.2v t rc 62.5 31.25 62.5 31.25 s 23 (d in may be left open) refresh current: self (s version only) average power supply current: cbr with i cc 8 all 300 300 300 300 a 4, 7 ras# ? t rass (min) and cas# held low; we# = v cc - 0.2v; a0-a11, oe# and d in = v cc - 0.2v or 0.2v (d in may be left open) capacitance (note: 6) parameter symbol max units input capacitance: address pins c i 1 5pf input capacitance: ras#, cas#, we#, oe# c i 2 7pf input/output capacitance: dq c io 7pf
6 4 meg x 4 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. d49_5v.p65 C rev. 5/00 ?2000, micron technology, inc. 4 meg x 4 fpm dram ac electrical characteristics (notes: 5, 6, 7, 8, 9, 10, 11, 12) [vcc (min) vcc vcc (max)] ac characteristics -5 -6 parameter symbol min max min max units notes access time from column address t aa 25 30 ns column-address hold time (referenced to ras#) t ar 38 45 ns column-address setup time t asc 0 0 ns row-address setup time t asr 0 0 ns column address to we# delay time t awd 42 49 ns 18 access time from cas# t cac 13 15 ns column-address hold time t cah 8 10 ns cas# pulse width t cas 8 10,000 10 10,000 ns cas# low to dont care during self refresh t chd 15 15 ns cas# hold time (cbr refresh) t chr 8 10 ns 4 cas# to output in low-z t clz 0 0 ns 22 cas# precharge time t cp 8 10 ns 13 access time from cas# precharge t cpa 28 35 ns cas# to ras# precharge time t crp 5 5 ns cas# hold time t csh 38 45 ns cas# setup time (cbr refresh) t csr 5 5 ns 4 cas# to we# delay time t cwd 28 35 ns 18 write command to cas# lead time t cwl 8 10 ns data-in hold time t dh 8 10 ns 19 data-in setup time t ds 0 0 ns 19 output disable t od 0 12 0 15 ns 22 output enable t oe 12 15 ns 20 oe# hold time from we# during t oeh 8 10 ns read-modify-write cycle output buffer turn-off delay t off 0 12 0 15 ns 17, 22 oe# setup prior to ras# during hidden refresh cycle t ord 0 0 ns fast-page-mode read or write cycle time t pc 20 25 ns fast-page-mode read-write cycle time t prwc 47 56 ns access time from ras# t rac 50 60 ns ras# to column-address delay time t rad 9 12 ns 15 row-address hold time t rah 9 10 ns ras# pulse width t ras 50 10,000 60 10,000 ns ras# pulse width (fast page mode) t rasp 50 125,000 60 125,000 ns ras# pulse width during self refresh t rass 100 100 s random read or write cycle time t rc 84 104 ns ras# to cas# delay time t rcd 11 14 ns 14 read command hold time (referenced to cas#) t rch 0 0 ns 16 read command setup time t rcs 0 0 ns refresh period (2,048 cycles) t ref 32 32 ms refresh period (4,096 cycles) t ref 64 64 ms
7 4 meg x 4 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. d49_5v.p65 C rev. 5/00 ?2000, micron technology, inc. 4 meg x 4 fpm dram ac electrical characteristics (notes: 5, 6, 7, 8, 9, 10, 11, 12) [vcc (min) vcc vcc (max)] ac characteristics -5 -6 parameter symbol min max min max units notes refresh period s version t ref 128 128 ms 140 ras# precharge time t rp 30 40 ns ras# to cas# precharge time t rpc 5 5 ns ras# precharge time exiting self refresh t rps 90 105 ns read command hold time (referenced to ras#) t rrh 0 0 ns 16 ras# hold time t rsh 13 15 ns read-write cycle time t rwc 116 140 ns ras# to we# delay time t rwd 67 79 ns 19 write command to ras# lead time t rwl 13 15 ns transition time (rise or fall) t t250250ns write command hold time t wch 8 10 ns write command hold time (referenced to ras#) t wcr 38 45 ns we# command setup time t wcs 0 0 ns 18 write command pulse width t wp 5 5 ns we# hold time (cbr refresh) t wrh 8 10 ns 4, 23 we# setup time (cbr refresh) t wrp 8 10 ns 4, 23
8 4 meg x 4 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. d49_5v.p65 C rev. 5/00 ?2000, micron technology, inc. 4 meg x 4 fpm dram notes 1. all voltages referenced to v ss . 2. this parameter is sampled. v cc = +3.3v or 5.0v; f = 1 mhz. 3. i cc is dependent on output loading and cycle rates. specified values are obtained with minimum cycle time and the outputs open. 4. enables on-chip refresh and address counters. 5. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured. 6. an initial pause of 100s is required after power- up, followed by eight ras# refresh cycles (ras#- only or cbr with we# high), before proper device operation is ensured. the eight ras# cycle wake-ups should be repeated any time the t ref refresh requirement is exceeded. 7. ac characteristics assume t t = 5ns. 8. v ih (min) and v il (max) are reference levels for measuring timing of input signals. transition times are measured between v ih and v il (or between v il and v ih ). 9. in addition to meeting the transition rate specification, all input signals must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. 10. if cas# = v ih , data output is high-z. 11. if cas# = v il , data output may contain data from the last valid read cycle. 12. measured with a load equivalent to two ttl gates, 100pf and v ol = 0.8v and v oh = 2v. 13. if cas# is low at the falling edge of ras#, q will be maintained from the previous cycle. to initiate a new cycle and clear the data-out buffer, cas# must be pulsed high for t cp. 14. the t rcd (max) limit is no longer specified. t rcd (max) was specified as a reference point only. if t rcd was greater than the specified t rcd (max) limit, then access time was con- trolled exclusively by t cac ( t rac [min] no longer applied). with or without the t rcd limit, t aa and t cac must always be met. 15. the t rad (max) limit is no longer specified. t rad (max) was specified as a reference point only. if t rad was greater than the specified t rad (max) limit, then access time was con- trolled exclusively by t aa ( t rac and t cac no longer applied). with or without the t rad (max) limit, t aa, t rac, and t cac must always be met. 16. either t rch or t rrh must be satisfied for a read cycle. 17. t off (max) defines the time at which the output achieves the open circuit condition and is not referenced to v oh or v ol . 18. t wcs, t rwd, t awd, and t cwd are not restrictive operating parameters. t wcs applies to early write cycles. t rwd, t awd, and t cwd apply to read-modify-write cycles. if t wcs ? t wcs (min), the cycle is an early write cycle and the data output will remain an open circuit throughout the entire cycle. if t rwd 3 t rwd (min), t awd 3 t awd (min), and t cwd 3 t cwd (min), the cycle is a read-modify- write and the data output will contain data read from the selected cell. if neither of the above conditions is met, the state of data-out is indeterminate. oe# held high and we# taken low after cas# goes low result in a late write (oe#-controlled) cycle. t wcs, t rwd, t cwd, and t awd are not applicable in a late write cycle. 19. these parameters are referenced to cas# leading edge in early write cycles and we# leading edge in late write or read-modify-write cycles. 20. if oe# is tied permanently low, late write, or read-modify-write operations are not permissible and should not be attempted. 21. a hidden refresh may also be performed after a write cycle. in this case, we# = low and oe# = high. 22. the 3ns minimum is a parameter guaranteed by design. 23. column address changed once each cycle. 24. v ih overshoot: v ih (max) = v cc + 2v for a pulse width 10ns, and the pulse width cannot be greater than one third of the cycle rate. v il undershoot: v il (min) = -2v for a pulse width 10ns, and the pu lse width cannot be greater than one third of the cycle rate.
9 4 meg x 4 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. d49_5v.p65 C rev. 5/00 ?2000, micron technology, inc. 4 meg x 4 fpm dram read cycle t rrh t clz t cac t rac t aa valid data open t off t rch row t rcs t asc t rah t rad t ar t cah t rcd t cas t rsh t csh t rp t rc t ras t crp t asr row open ras# v v ih il cas# v v ih il addr v v ih il dq v v ioh iol v v ih il column we# dont care undefined -5 -6 symbol min max min max units t off 0 12 0 15 ns t r a c 50 60 n s t rad 9 12 ns t rah 9 10 ns t ras 50 10,000 60 10,000 ns t rc 84 104 ns t r c d 11 14 n s t rch 0 0 ns t rcs 0 0 ns t rp 30 40 n s t rrh 0 0 ns t rsh 13 15 ns timing parameters -5 -6 symbol min max min max units t a a 25 30 n s t ar 38 45 n s t asc 0 0 ns t asr 0 0 ns t c a c 13 15 n s t cah 8 10 ns t cas 8 10,000 10 10,000 ns t clz 0 0 ns t crp 5 5 ns t c s h 38 45 n s t od 0 12 0 15 ns t oe 12 15 n s
10 4 meg x 4 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. d49_5v.p65 C rev. 5/00 ?2000, micron technology, inc. 4 meg x 4 fpm dram early write cycle dont care undefined v v ih il cas# valid data row column row t ds t dh t wp t wch t wcs t wcr t rwl t cwl t cah t asc t rah t asr t rad t ar t cas t rsh t csh t rcd t crp t ras t rc t rp v v ih il addr v v ih il we# v v ih il dq v v ioh iol ras# -5 -6 symbol min max min max units t rah 9 10 ns t ras 50 10,000 60 10,000 ns t rc 84 104 ns t r c d 11 14 n s t rp 30 40 n s t rsh 13 15 ns t rwl 13 15 n s t wch 8 10 ns t w c r 38 45 n s t wcs 0 0 ns t wp 5 5 ns timing parameters -5 -6 symbol min max min max units t ar 38 45 n s t asc 0 0 ns t asr 0 0 ns t cah 8 10 ns t cas 8 10,000 10 10,000 ns t crp 5 5 ns t c s h 38 45 n s t cwl 8 10 ns t dh 8 10 ns t ds 0 0 ns t rad 9 12 ns
11 4 meg x 4 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. d49_5v.p65 C rev. 5/00 ?2000, micron technology, inc. 4 meg x 4 fpm dram read-write cycle (late write and read-modify-write cycles) valid d out valid d in row column row v v ih il cas# v v ih il addr v v ih il v v ih il dq v v ioh iol v v ih il ras# open open t oe t od t cac t rac t aa t clz t ds t dh t awd t wp t rwl t cwl t cwd t rwd t rcs t asc t cah t ar t asr t rad t crp t rcd t cas t rsh t csh t ras t rwc t rp t rah oe# t oeh we# dont care undefined -5 -6 symbol min max min max units t od 0 12 0 15 ns t oe 12 15 n s t oeh 8 10 ns t r a c 50 60 n s t rad 9 12 ns t rah 9 10 ns t ras 50 10,000 60 10,000 ns t r c d 11 14 n s t rcs 0 0 ns t rp 30 40 n s t rsh 13 15 ns t rwc 116 140 ns t rwd 67 79 ns t rwl 13 15 n s t wp 5 5 ns timing parameters -5 -6 symbol min max min max units t a a 25 30 n s t ar 38 45 n s t asc 0 0 ns t asr 0 0 ns t a w d 42 49 n s t c a c 13 15 n s t cah 8 10 ns t cas 8 10,000 10 10,000 ns t clz 0 0 ns t crp 5 5 ns t c s h 38 45 n s t cwd 28 35 ns t cwl 8 10 ns t dh 8 10 ns t ds 0 0 ns
12 4 meg x 4 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. d49_5v.p65 C rev. 5/00 ?2000, micron technology, inc. 4 meg x 4 fpm dram valid data valid data valid data column column column row row t rcs t cah t asc t cp t cas t rsh t cp t cas t cp t cas t rcd t crp t pc t csh t rasp t rp t cah t asc t cah t asc t ar t rah t rad t asr t rcs t rch t rch t rcs t rrh t rch t off t cac t cpa t aa t clz t off t cac t cpa t aa t clz t off t cac t rac t aa t clz t oe t od t oe t od t oe t od open open v v ih il cas# v v ih il addr v v ih il we# v v ih il dq v v ioh iol v v ih il ras# oe# dont care undefined fast-page-mode read cycle -5 -6 symbol min max min max units t oe 12 15 n s t off 0 12 0 15 ns t pc 20 25 n s t r a c 50 60 n s t rad 9 12 ns t rah 9 10 ns t rasp 50 125,000 60 125,000 ns t r c d 11 14 n s t rch 0 0 ns t rcs 0 0 ns t rp 30 40 n s t rrh 0 0 ns t rsh 13 15 ns timing parameters -5 -6 symbol min max min max units t a a 25 30 n s t ar 38 45 n s t asc 0 0 ns t asr 0 0 ns t c a c 13 15 n s t cah 8 10 ns t cas 8 10,000 10 10,000 ns t clz 0 0 ns t cp 8 10 ns t cpa 28 35 n s t crp 5 5 ns t c s h 38 45 n s t od 0 12 0 15 ns
13 4 meg x 4 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. d49_5v.p65 C rev. 5/00 ?2000, micron technology, inc. 4 meg x 4 fpm dram fast-page-mode early write cycle t ds t dh t ds t dh t ds t dh t wcr valid data valid data valid data t rwl t wp t cwl t wch t wcs t wp t cwl t wch t wcs t wp t cwl t wch t wcs t cah t asc t cah t asc t cah t asc t rah t asr t rad t ar column column column row row t cp t cas t rsh t cp t cas t cp t cas t rcd t crp t pc t csh t rasp t rp v v ih il cas# v v ih il addr v v ih il we# v v ih il dq v v ioh iol ras# oe# v v ih il dont care undefined -5 -6 symbol min max min max units t rad 9 12 ns t rah 9 10 ns t rasp 50 125,000 60 125,000 ns t r c d 11 14 n s t rp 30 40 n s t rsh 13 15 ns t rwl 13 15 n s t wch 8 10 ns t w c r 38 45 n s t wcs 0 0 ns t wp 5 5 ns timing parameters -5 -6 symbol min max min max units t ar 38 45 n s t asc 0 0 ns t asr 0 0 ns t cah 8 10 ns t cas 8 10,000 10 10,000 ns t cp 8 10 ns t crp 5 5 ns t c s h 38 45 n s t cwl 8 10 ns t dh 8 10 ns t ds 0 0 ns t pc 20 25 n s
14 4 meg x 4 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. d49_5v.p65 C rev. 5/00 ?2000, micron technology, inc. 4 meg x 4 fpm dram dont care undefined t oe t oe t oe open d out valid d in valid d out valid d in valid d out valid d in valid open t dh t ds t aa t cpa t clz t cac t dh t ds t aa t cpa t clz t cac t dh t ds t aa t clz t cac t rac t wp t cwl t rwl t cwd t awd t wp t cwl t cwd t awd t wp t cwl t cwd t awd t rcs t rwd t asr t rah t asc t rad t ar t cah t asc t cah t asc t cah t cp t cas t rsh t cp t rp t rasp t cas t cp t cas t rcd t csh t pc note 1 t crp row column column column row v v ih il cas# v v ih il addr v v ih il v v ih il dq v v ioh iol v v ih il ras# oe# we# t prwc t oeh t od t od t od fast-page-mode read-write cycle (late write and read-modify-write cycles) note: 1. t pc is for late write only. -5 -6 symbol min max min max units t od 0 12 0 15 ns t oe 12 15 n s t oeh 8 10 ns t pc 20 25 n s t prwc 47 56 ns t r a c 50 60 n s t rad 9 12 ns t rah 9 10 ns t rasp 50 125,000 60 125,000 ns t r c d 11 14 n s t rcs 0 0 ns t rp 30 40 n s t rsh 13 15 ns t rwd 67 79 ns t rwl 13 15 n s t wp 5 5 ns timing parameters -5 -6 symbol min max min max units t a a 25 30 n s t ar 38 45 n s t asc 0 0 ns t asr 0 0 ns t a w d 42 49 n s t c a c 13 15 n s t cah 8 10 ns t cas 8 10,000 10 10,000 ns t clz 0 0 ns t cp 8 10 ns t cpa 28 35 n s t crp 5 5 ns t c s h 38 45 n s t cwd 28 35 ns t cwl 8 10 ns t dh 8 10 ns t ds 0 0 ns
15 4 meg x 4 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. d49_5v.p65 C rev. 5/00 ?2000, micron technology, inc. 4 meg x 4 fpm dram fast-page-mode read early write cycle (pseudo read-modify-write) row valid data valid data open t crp t rcd t cas t rsh t rasp t rp t pc t asc t cah t ar t asr t rad t rah t wcs t wp t rwl t rcs t dh t ds t cac t off v v ih il cas# v v ih il addr v v ih il ras# dq v v oh ol we# v v ih il t csh column t cp t cp t asc t cah t cwl t wch t clz t aa rac dont care undefined t note 1 row column t cas note: 1. do not drive data prior to tristate. -5 -6 symbol min max min max units t off 0 12 0 15 ns t pc 20 25 n s t r a c 50 60 n s t rad 9 12 ns t rah 9 10 ns t rasp 50 125,000 60 125,000 ns t r c d 11 14 n s t rcs 0 0 ns t rp 30 40 n s t rsh 13 15 ns t rwl 13 15 n s t wch 8 10 ns t wcs 0 0 ns t wp 5 5 ns timing parameters -5 -6 symbol min max min max units t a a 25 30 n s t ar 38 45 n s t asc 0 0 ns t asr 0 0 ns t c a c 13 15 n s t cah 8 10 ns t cas 8 10,000 10 10,000 ns t clz 0 0 ns t cp 8 10 ns t crp 5 5 ns t c s h 38 45 n s t cwl 8 10 ns t dh 8 10 ns t ds 0 0 ns
16 4 meg x 4 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. d49_5v.p65 C rev. 5/00 ?2000, micron technology, inc. 4 meg x 4 fpm dram ras#-only refresh cycle (oe# and we# = dont care) row v v ih il cas# v v ih il addr v v ih il ras# t rc t ras t rp t crp t asr t rah row open dq v v oh ol t rpc cbr refresh cycle (addresses and oe# = dont care) t rp v v ih il ras# t ras open t chr t csr v v ih il v v oh ol cas# dq t rp t ras t rpc t csr t rpc t chr t cp v v ih il t wrp t wrh t wrp t wrh we# dont care undefined note 1 -5 -6 symbol min max min max units timing parameters -5 -6 symbol min max min max units t asr 0 0 ns t chr 8 10 ns t cp 8 10 ns t crp 5 5 ns t csr 5 5 ns t rah 9 10 ns t ras 50 10,000 60 10,000 ns t rc 84 104 ns t rp 30 40 n s t rpc 5 5 ns t wrh 8 10 ns t wrp 8 10 ns note: 1. end of cbr refresh cycle.
17 4 meg x 4 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. d49_5v.p65 C rev. 5/00 ?2000, micron technology, inc. 4 meg x 4 fpm dram dont care undefined t clz t off open valid data open column row t cac t rac t aa t cah t asc t rah t asr t rad t ar t crp t rcd t rsh t ras t rp t chr t ras dqx v v ioh iol v v ih il addr v v ih il v v ih il ras# t oe t od casl#/cash# v v ih il oe# t ord hidden refresh cycle 1 (we# = high; oe# = low) -5 -6 symbol min max min max units t oe 12 15 n s t off 0 12 0 15 ns t ord 0 0 ns t r a c 50 60 n s t rad 9 12 ns t rah 9 10 ns t ras 50 10,000 60 10,000 ns t r c d 11 14 n s t rp 30 40 n s t rsh 13 15 ns timing parameters -5 -6 symbol min max min max units t a a 25 30 n s t ar 38 45 n s t asc 0 0 ns t asr 0 0 ns t c a c 13 15 n s t cah 8 10 ns t chr 8 10 ns t clz 0 0 ns t crp 5 5 ns t od 0 12 0 15 ns note: 1. a hidden refresh may also be performed after a write cycle. in this case, we# is low and oe# is high.
18 4 meg x 4 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. d49_5v.p65 C rev. 5/00 ?2000, micron technology, inc. 4 meg x 4 fpm dram self refresh cycle (addresses and oe# = dont care) t rp v v ih il ras# t ras open t chr t csr v v ih il cas# q t rp t ras t rpc t csr t rpc t chr t cp v v ih il t wrp t wrh t wrp t wrh we# dont care undefined note: 1. once t rass (min) is met and ras# remains low, the dram will enter self refresh mode. 2. once t rps is satisfied, a complete burst of all rows should be executed if ras#-only or burst cbr refresh is used. -5 -6 symbol min max min max units timing parameters -5 -6 symbol min max min max units t c h d 15 15 n s t cp 8 10 ns t csr 5 5 ns t rass 100 100 s t rp 30 40 n s t rpc 5 5 ns t rps 90 105 ns t wrh 8 10 ns t wrp 8 10 ns
19 4 meg x 4 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. d49_5v.p65 C rev. 5/00 ?2000, micron technology, inc. 4 meg x 4 fpm dram 24/26-pin plastic soj (300 mil) r .299 (7.59) .305 (7.75) .679 (17.25) .673 (17.09) .340 (8.64) .330 (8.38) .050 (1.27) typ .600 (15.24) typ pin #1 index .020 (0.51) .015 (0.38) .132 (3.35) .142 (3.61) .105 (2.67) .090 (2.29) .260 (6.61) .275 (6.99) .030 (0.76) .040 (1.02) seating plane .112 (2.84) .102 (2.59) .037 (0.94) max dambar protrusion .026 (0.66) .032 (0.81) note: 1. all dimensions in inches (millimeters) max or typical where noted. min 2. package width and length do not include mold protrusion; allowable mold protrusion is .01" per side.
20 4 meg x 4 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. d49_5v.p65 C rev. 5/00 ?2000, micron technology, inc. 4 meg x 4 fpm dram 24/26-pin plastic tsop (300 mil) .047 (1.20) max .367 (9.32) .359 (9.12) .302 (7.67) .298 (7.57) .050 (1.27) typ 1 26 13 .678 (17.23) .672 (17.07) .020 (0.50) .012 (0.30) pin #1 index see detail a .007 (0.18) .005 (0.13) .004 (0.10) .024 (0.60) .016 (0.40) .008 (0.20) .002 (0.05) detail a .010 (0.25) .0315 (0.80) typ gage plane seating plane note: 1. all dimensions in inches (millimeters) max or typical where noted. min 2. package width and length do not include mold protrusion; allowable mold protrusion is .01" per side. 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www.micron.com, customer comment line: 800-932-4992 micron is a registered trademark of micron technology, inc.

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